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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Rev 356

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132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 7940d 00h /ethmac/trunk/rtl/verilog/eth_registers.v
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 8054d 04h /ethmac/trunk/rtl/verilog/eth_registers.v
74 Reset values are passed to registers through parameters mohor 8109d 02h /ethmac/trunk/rtl/verilog/eth_registers.v
69 Define missmatch fixed. mohor 8118d 05h /ethmac/trunk/rtl/verilog/eth_registers.v
68 Registered trimmed. Unused registers removed. mohor 8119d 04h /ethmac/trunk/rtl/verilog/eth_registers.v
56 File format fixed a bit. mohor 8120d 07h /ethmac/trunk/rtl/verilog/eth_registers.v
52 Modified for Address Checking,
addition of eth_addrcheck.v
billditt 8120d 22h /ethmac/trunk/rtl/verilog/eth_registers.v
46 HASH0 and HASH1 registers added. mohor 8123d 01h /ethmac/trunk/rtl/verilog/eth_registers.v
37 Link in the header changed. mohor 8143d 08h /ethmac/trunk/rtl/verilog/eth_registers.v
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).
mohor 8192d 03h /ethmac/trunk/rtl/verilog/eth_registers.v

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