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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_registers.v] - Rev 367

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140 Syntax error fixed. mohor 7923d 19h /ethmac/trunk/rtl/verilog/eth_registers.v
139 Synchronous reset added to all registers. Defines used for width. r_MiiMRst
changed from bit position 10 to 9.
mohor 7923d 19h /ethmac/trunk/rtl/verilog/eth_registers.v
132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 7925d 23h /ethmac/trunk/rtl/verilog/eth_registers.v
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 8040d 03h /ethmac/trunk/rtl/verilog/eth_registers.v
74 Reset values are passed to registers through parameters mohor 8095d 01h /ethmac/trunk/rtl/verilog/eth_registers.v
69 Define missmatch fixed. mohor 8104d 04h /ethmac/trunk/rtl/verilog/eth_registers.v
68 Registered trimmed. Unused registers removed. mohor 8105d 03h /ethmac/trunk/rtl/verilog/eth_registers.v
56 File format fixed a bit. mohor 8106d 06h /ethmac/trunk/rtl/verilog/eth_registers.v
52 Modified for Address Checking,
addition of eth_addrcheck.v
billditt 8106d 21h /ethmac/trunk/rtl/verilog/eth_registers.v
46 HASH0 and HASH1 registers added. mohor 8109d 00h /ethmac/trunk/rtl/verilog/eth_registers.v

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