URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_rxaddrcheck.v] - Rev 350

Rev	Log message	Author	Age	Path
341	Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short	olof	4685d 17h	/ethmac/trunk/rtl/verilog/eth_rxaddrcheck.v
338		root	5479d 19h	/ethmac/trunk/rtl/verilog/eth_rxaddrcheck.v
335	New directory structure.	root	5537d 00h	/ethmac/trunk/rtl/verilog/eth_rxaddrcheck.v
261	Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort synchronized.	mohor	7836d 09h	/ethmac/trunk/rtl/verilog/eth_rxaddrcheck.v
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	7838d 17h	/ethmac/trunk/rtl/verilog/eth_rxaddrcheck.v
148	Bug when last byte of destination address was not checked fixed.	mohor	7914d 16h	/ethmac/trunk/rtl/verilog/eth_rxaddrcheck.v
93	When in promiscous mode some frames were not received correctly. Fixed.	mohor	8082d 19h	/ethmac/trunk/rtl/verilog/eth_rxaddrcheck.v
85	Log info was missing.	mohor	8100d 13h	/ethmac/trunk/rtl/verilog/eth_rxaddrcheck.v
83	MAC address recognition was not correct (bytes swaped).	mohor	8100d 13h	/ethmac/trunk/rtl/verilog/eth_rxaddrcheck.v
75	r_Bro is used for accepting/denying frames	mohor	8104d 18h	/ethmac/trunk/rtl/verilog/eth_rxaddrcheck.v
65	Testbench fixed, code simplified, unused signals removed.	mohor	8115d 03h	/ethmac/trunk/rtl/verilog/eth_rxaddrcheck.v
50	checks destination address for Unicast, Multicast and Broadcast ops	billditt	8116d 15h	/ethmac/trunk/rtl/verilog/eth_rxaddrcheck.v