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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_rxstatem.v] - Rev 346


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Rev Log message Author Age Path
346 Updated project location olof 4459d 16h /ethmac/trunk/rtl/verilog/eth_rxstatem.v
338 root 5263d 19h /ethmac/trunk/rtl/verilog/eth_rxstatem.v
335 New directory structure. root 5321d 00h /ethmac/trunk/rtl/verilog/eth_rxstatem.v
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 7628d 12h /ethmac/trunk/rtl/verilog/eth_rxstatem.v
37 Link in the header changed. mohor 7923d 00h /ethmac/trunk/rtl/verilog/eth_rxstatem.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 8019d 01h /ethmac/trunk/rtl/verilog/eth_rxstatem.v
21 Status signals changed, Adress decoding changed, interrupt controller
mohor 8019d 22h /ethmac/trunk/rtl/verilog/eth_rxstatem.v
18 Few little NCSIM warnings fixed. mohor 8056d 20h /ethmac/trunk/rtl/verilog/eth_rxstatem.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 8092d 19h /ethmac/trunk/rtl/verilog/eth_rxstatem.v

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