OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_spram_256x32.v] - Rev 358

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4443d 06h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4443d 06h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4443d 07h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
354 Whitespace cleanup olof 4443d 09h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
352 Removed delayed assignments from rtl code olof 4449d 16h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
346 Updated project location olof 4460d 09h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
338 root 5264d 11h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
335 New directory structure. root 5321d 16h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
330 Warning fixes. igorm 6798d 14h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 7242d 14h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
306 Lapsus fixed (!we -> ~we). simons 7243d 12h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7265d 08h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
302 mbist signals updated according to newest convention markom 7291d 19h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
297 Artisan ram instance added. simons 7355d 10h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
227 Changed BIST scan signals. tadejm 7655d 09h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
210 BIST added. mohor 7663d 10h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7680d 08h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7742d 10h /ethmac/trunk/rtl/verilog/eth_spram_256x32.v

powered by: WebSVN 2.1.0

© copyright 1999-2023 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.