URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_spram_256x32.v] - Rev 306

Rev	Log message	Author	Age	Path
306	Lapsus fixed (!we -> ~we).	simons	7448d 04h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7470d 00h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v
302	mbist signals updated according to newest convention	markom	7496d 11h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v
297	Artisan ram instance added.	simons	7560d 02h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v
227	Changed BIST scan signals.	tadejm	7860d 01h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v
210	BIST added.	mohor	7868d 02h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v
204	ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).	mohor	7885d 00h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v
122	ethernet spram added. So far a generic ram and xilinx RAMB4 are used.	mohor	7947d 02h	/ethmac/trunk/rtl/verilog/eth_spram_256x32.v