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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_transmitcontrol.v] - Rev 353

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Rev Log message Author Age Path
353 Inherit fixes for bit width of constants from ORPSoC olof 3024d 12h /ethmac/trunk/rtl/verilog/eth_transmitcontrol.v
352 Removed delayed assignments from rtl code olof 3028d 18h /ethmac/trunk/rtl/verilog/eth_transmitcontrol.v
346 Updated project location olof 3039d 11h /ethmac/trunk/rtl/verilog/eth_transmitcontrol.v
338 root 3843d 13h /ethmac/trunk/rtl/verilog/eth_transmitcontrol.v
335 New directory structure. root 3900d 18h /ethmac/trunk/rtl/verilog/eth_transmitcontrol.v
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.
mohor 6201d 04h /ethmac/trunk/rtl/verilog/eth_transmitcontrol.v
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.
mohor 6202d 11h /ethmac/trunk/rtl/verilog/eth_transmitcontrol.v
37 Link in the header changed. mohor 6502d 18h /ethmac/trunk/rtl/verilog/eth_transmitcontrol.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 6598d 20h /ethmac/trunk/rtl/verilog/eth_transmitcontrol.v
18 Few little NCSIM warnings fixed. mohor 6636d 14h /ethmac/trunk/rtl/verilog/eth_transmitcontrol.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 6672d 14h /ethmac/trunk/rtl/verilog/eth_transmitcontrol.v

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