OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_txethmac.v] - Rev 353

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
353 Inherit fixes for bit width of constants from ORPSoC olof 3028d 08h /ethmac/trunk/rtl/verilog/eth_txethmac.v
352 Removed delayed assignments from rtl code olof 3032d 14h /ethmac/trunk/rtl/verilog/eth_txethmac.v
349 Make all parameters configurable from top level olof 3042d 05h /ethmac/trunk/rtl/verilog/eth_txethmac.v
346 Updated project location olof 3043d 06h /ethmac/trunk/rtl/verilog/eth_txethmac.v
338 root 3847d 09h /ethmac/trunk/rtl/verilog/eth_txethmac.v
335 New directory structure. root 3904d 14h /ethmac/trunk/rtl/verilog/eth_txethmac.v
328 Delayed CRC fixed. igorm 5381d 13h /ethmac/trunk/rtl/verilog/eth_txethmac.v
277 When padding was enabled and crc disabled, frame was not ended correctly. mohor 6134d 11h /ethmac/trunk/rtl/verilog/eth_txethmac.v
79 RetryCntLatched was unused and removed from design mohor 6472d 08h /ethmac/trunk/rtl/verilog/eth_txethmac.v
72 Retry is not activated when a Tx Underrun occured mohor 6476d 11h /ethmac/trunk/rtl/verilog/eth_txethmac.v
43 Tx status is written back to the BD. mohor 6487d 15h /ethmac/trunk/rtl/verilog/eth_txethmac.v
37 Link in the header changed. mohor 6506d 14h /ethmac/trunk/rtl/verilog/eth_txethmac.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 6602d 15h /ethmac/trunk/rtl/verilog/eth_txethmac.v
18 Few little NCSIM warnings fixed. mohor 6640d 10h /ethmac/trunk/rtl/verilog/eth_txethmac.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 6676d 09h /ethmac/trunk/rtl/verilog/eth_txethmac.v

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.