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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_txstatem.v] - Rev 236

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236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7786d 11h /ethmac/trunk/rtl/verilog/eth_txstatem.v
37 Link in the header changed. mohor 8066d 14h /ethmac/trunk/rtl/verilog/eth_txstatem.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 8162d 15h /ethmac/trunk/rtl/verilog/eth_txstatem.v
18 Few little NCSIM warnings fixed. mohor 8200d 10h /ethmac/trunk/rtl/verilog/eth_txstatem.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 8236d 09h /ethmac/trunk/rtl/verilog/eth_txstatem.v

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