OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_txstatem.v] - Rev 346

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
346 Updated project location olof 3469d 04h /ethmac/trunk/rtl/verilog/eth_txstatem.v
338 root 4273d 06h /ethmac/trunk/rtl/verilog/eth_txstatem.v
335 New directory structure. root 4330d 11h /ethmac/trunk/rtl/verilog/eth_txstatem.v
276 Defer indication changed. tadejm 6560d 08h /ethmac/trunk/rtl/verilog/eth_txstatem.v
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6652d 09h /ethmac/trunk/rtl/verilog/eth_txstatem.v
37 Link in the header changed. mohor 6932d 11h /ethmac/trunk/rtl/verilog/eth_txstatem.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 7028d 13h /ethmac/trunk/rtl/verilog/eth_txstatem.v
18 Few little NCSIM warnings fixed. mohor 7066d 07h /ethmac/trunk/rtl/verilog/eth_txstatem.v
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 7102d 07h /ethmac/trunk/rtl/verilog/eth_txstatem.v

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.