OpenCores

URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_txstatem.v] - Rev 368

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Rev	Log message	Author	Age	Path
352	Removed delayed assignments from rtl code	olof	4664d 23h	/ethmac/trunk/rtl/verilog/eth_txstatem.v
346	Updated project location	olof	4675d 15h	/ethmac/trunk/rtl/verilog/eth_txstatem.v
338		root	5479d 18h	/ethmac/trunk/rtl/verilog/eth_txstatem.v
335	New directory structure.	root	5536d 23h	/ethmac/trunk/rtl/verilog/eth_txstatem.v
276	Defer indication changed.	tadejm	7766d 19h	/ethmac/trunk/rtl/verilog/eth_txstatem.v
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	7858d 20h	/ethmac/trunk/rtl/verilog/eth_txstatem.v
37	Link in the header changed.	mohor	8138d 22h	/ethmac/trunk/rtl/verilog/eth_txstatem.v
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8235d 00h	/ethmac/trunk/rtl/verilog/eth_txstatem.v
18	Few little NCSIM warnings fixed.	mohor	8272d 19h	/ethmac/trunk/rtl/verilog/eth_txstatem.v
15	A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). Include files fixed to contain no path. File names and module names changed ta have a eth_ prologue in the name. File eth_timescale.v is used to define timescale All pin names on the top module are changed to contain _I, _O or _OE at the end. Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O and Mdo_OE. The bidirectional signal must be created on the top level. This is done due to the ASIC tools.	mohor	8308d 18h	/ethmac/trunk/rtl/verilog/eth_txstatem.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.