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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 115

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Rev Log message Author Age Path
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7975d 09h /ethmac/trunk/rtl/verilog/eth_wishbone.v
113 RxPointer bug fixed. mohor 7982d 23h /ethmac/trunk/rtl/verilog/eth_wishbone.v
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7983d 12h /ethmac/trunk/rtl/verilog/eth_wishbone.v
111 Master state machine had a bug when switching from master write to
master read.
mohor 7984d 02h /ethmac/trunk/rtl/verilog/eth_wishbone.v
110 m_wb_cyc_o signal released after every single transfer. mohor 7984d 05h /ethmac/trunk/rtl/verilog/eth_wishbone.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8051d 15h /ethmac/trunk/rtl/verilog/eth_wishbone.v
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 8060d 17h /ethmac/trunk/rtl/verilog/eth_wishbone.v
97 Small typo fixed. lampret 8086d 09h /ethmac/trunk/rtl/verilog/eth_wishbone.v
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.
mohor 8090d 09h /ethmac/trunk/rtl/verilog/eth_wishbone.v
91 Comments in Slovene language removed. mohor 8096d 13h /ethmac/trunk/rtl/verilog/eth_wishbone.v
90 casex changed with case, fifo reset changed. mohor 8096d 13h /ethmac/trunk/rtl/verilog/eth_wishbone.v
88 rx_fifo was not always cleared ok. Fixed. mohor 8106d 09h /ethmac/trunk/rtl/verilog/eth_wishbone.v
87 Status was not latched correctly sometimes. Fixed. mohor 8106d 12h /ethmac/trunk/rtl/verilog/eth_wishbone.v
86 Big Endian problem when sending frames fixed. mohor 8107d 18h /ethmac/trunk/rtl/verilog/eth_wishbone.v
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.
mohor 8113d 06h /ethmac/trunk/rtl/verilog/eth_wishbone.v
80 Small fixes for external/internal DMA missmatches. mohor 8117d 08h /ethmac/trunk/rtl/verilog/eth_wishbone.v
77 Interrupts changed mohor 8117d 09h /ethmac/trunk/rtl/verilog/eth_wishbone.v
64 Status was not written correctly when frames were discarted because of
address mismatch.
mohor 8128d 08h /ethmac/trunk/rtl/verilog/eth_wishbone.v
61 RxStartFrm cleared when abort or retry comes. mohor 8128d 13h /ethmac/trunk/rtl/verilog/eth_wishbone.v
60 Changes that were lost when updating from 1.5 to 1.8 fixed. mohor 8128d 13h /ethmac/trunk/rtl/verilog/eth_wishbone.v

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