URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 127

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
127	WriteRxDataToMemory signal changed so end of frame (when last word is written to fifo) is changed.	mohor	8369d 00h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	8371d 03h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
118	ShiftEnded synchronization changed.	mohor	8374d 17h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
115	RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.	mohor	8376d 02h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
113	RxPointer bug fixed.	mohor	8383d 15h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
112	Previous bug wasn't succesfully removed. Now fixed.	mohor	8384d 05h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
111	Master state machine had a bug when switching from master write to master read.	mohor	8384d 18h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
110	m_wb_cyc_o signal released after every single transfer.	mohor	8384d 21h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8452d 08h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8461d 09h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
97	Small typo fixed.	lampret	8487d 02h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
96	Any address can be used for Tx and Rx BD pointers. Address does not need to be aligned.	mohor	8491d 02h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
91	Comments in Slovene language removed.	mohor	8497d 05h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
90	casex changed with case, fifo reset changed.	mohor	8497d 05h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
88	rx_fifo was not always cleared ok. Fixed.	mohor	8507d 02h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
87	Status was not latched correctly sometimes. Fixed.	mohor	8507d 04h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
86	Big Endian problem when sending frames fixed.	mohor	8508d 11h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
82	Byte ordering changed (Big Endian used). casex changed with case because Xilinx Foundation had problems. Tested in HW. It WORKS.	mohor	8513d 23h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
80	Small fixes for external/internal DMA missmatches.	mohor	8518d 01h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
77	Interrupts changed	mohor	8518d 02h	/ethmac/trunk/rtl/verilog/eth_wishbone.v

1 2 Next >

Show All

Browse

Tools

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 127

Filtering Options