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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 210

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210 BIST added. mohor 7856d 03h /ethmac/trunk/rtl/verilog/eth_wishbone.v
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7885d 05h /ethmac/trunk/rtl/verilog/eth_wishbone.v
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.
mohor 7886d 05h /ethmac/trunk/rtl/verilog/eth_wishbone.v
164 Ethernet debug registers removed. mohor 7886d 09h /ethmac/trunk/rtl/verilog/eth_wishbone.v
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.
mohor 7888d 03h /ethmac/trunk/rtl/verilog/eth_wishbone.v
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.
mohor 7892d 00h /ethmac/trunk/rtl/verilog/eth_wishbone.v
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.
mohor 7913d 00h /ethmac/trunk/rtl/verilog/eth_wishbone.v
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 7933d 01h /ethmac/trunk/rtl/verilog/eth_wishbone.v
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7935d 04h /ethmac/trunk/rtl/verilog/eth_wishbone.v
118 ShiftEnded synchronization changed. mohor 7938d 18h /ethmac/trunk/rtl/verilog/eth_wishbone.v
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7940d 03h /ethmac/trunk/rtl/verilog/eth_wishbone.v
113 RxPointer bug fixed. mohor 7947d 16h /ethmac/trunk/rtl/verilog/eth_wishbone.v
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7948d 06h /ethmac/trunk/rtl/verilog/eth_wishbone.v
111 Master state machine had a bug when switching from master write to
master read.
mohor 7948d 19h /ethmac/trunk/rtl/verilog/eth_wishbone.v
110 m_wb_cyc_o signal released after every single transfer. mohor 7948d 22h /ethmac/trunk/rtl/verilog/eth_wishbone.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8016d 09h /ethmac/trunk/rtl/verilog/eth_wishbone.v
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 8025d 10h /ethmac/trunk/rtl/verilog/eth_wishbone.v
97 Small typo fixed. lampret 8051d 03h /ethmac/trunk/rtl/verilog/eth_wishbone.v
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.
mohor 8055d 03h /ethmac/trunk/rtl/verilog/eth_wishbone.v
91 Comments in Slovene language removed. mohor 8061d 06h /ethmac/trunk/rtl/verilog/eth_wishbone.v
90 casex changed with case, fifo reset changed. mohor 8061d 06h /ethmac/trunk/rtl/verilog/eth_wishbone.v
88 rx_fifo was not always cleared ok. Fixed. mohor 8071d 03h /ethmac/trunk/rtl/verilog/eth_wishbone.v
87 Status was not latched correctly sometimes. Fixed. mohor 8071d 05h /ethmac/trunk/rtl/verilog/eth_wishbone.v
86 Big Endian problem when sending frames fixed. mohor 8072d 12h /ethmac/trunk/rtl/verilog/eth_wishbone.v
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.
mohor 8078d 00h /ethmac/trunk/rtl/verilog/eth_wishbone.v
80 Small fixes for external/internal DMA missmatches. mohor 8082d 02h /ethmac/trunk/rtl/verilog/eth_wishbone.v
77 Interrupts changed mohor 8082d 03h /ethmac/trunk/rtl/verilog/eth_wishbone.v
64 Status was not written correctly when frames were discarted because of
address mismatch.
mohor 8093d 02h /ethmac/trunk/rtl/verilog/eth_wishbone.v
61 RxStartFrm cleared when abort or retry comes. mohor 8093d 07h /ethmac/trunk/rtl/verilog/eth_wishbone.v
60 Changes that were lost when updating from 1.5 to 1.8 fixed. mohor 8093d 07h /ethmac/trunk/rtl/verilog/eth_wishbone.v

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