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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 210

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Rev Log message Author Age Path
90 casex changed with case, fifo reset changed. mohor 8069d 21h /ethmac/trunk/rtl/verilog/eth_wishbone.v
88 rx_fifo was not always cleared ok. Fixed. mohor 8079d 17h /ethmac/trunk/rtl/verilog/eth_wishbone.v
87 Status was not latched correctly sometimes. Fixed. mohor 8079d 20h /ethmac/trunk/rtl/verilog/eth_wishbone.v
86 Big Endian problem when sending frames fixed. mohor 8081d 03h /ethmac/trunk/rtl/verilog/eth_wishbone.v
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.
mohor 8086d 14h /ethmac/trunk/rtl/verilog/eth_wishbone.v
80 Small fixes for external/internal DMA missmatches. mohor 8090d 17h /ethmac/trunk/rtl/verilog/eth_wishbone.v
77 Interrupts changed mohor 8090d 17h /ethmac/trunk/rtl/verilog/eth_wishbone.v
64 Status was not written correctly when frames were discarted because of
address mismatch.
mohor 8101d 16h /ethmac/trunk/rtl/verilog/eth_wishbone.v
61 RxStartFrm cleared when abort or retry comes. mohor 8101d 21h /ethmac/trunk/rtl/verilog/eth_wishbone.v
60 Changes that were lost when updating from 1.5 to 1.8 fixed. mohor 8101d 22h /ethmac/trunk/rtl/verilog/eth_wishbone.v

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