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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 219

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91 Comments in Slovene language removed. mohor 8045d 06h /ethmac/trunk/rtl/verilog/eth_wishbone.v
90 casex changed with case, fifo reset changed. mohor 8045d 06h /ethmac/trunk/rtl/verilog/eth_wishbone.v
88 rx_fifo was not always cleared ok. Fixed. mohor 8055d 03h /ethmac/trunk/rtl/verilog/eth_wishbone.v
87 Status was not latched correctly sometimes. Fixed. mohor 8055d 05h /ethmac/trunk/rtl/verilog/eth_wishbone.v
86 Big Endian problem when sending frames fixed. mohor 8056d 12h /ethmac/trunk/rtl/verilog/eth_wishbone.v
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.
mohor 8062d 00h /ethmac/trunk/rtl/verilog/eth_wishbone.v
80 Small fixes for external/internal DMA missmatches. mohor 8066d 02h /ethmac/trunk/rtl/verilog/eth_wishbone.v
77 Interrupts changed mohor 8066d 03h /ethmac/trunk/rtl/verilog/eth_wishbone.v
64 Status was not written correctly when frames were discarted because of
address mismatch.
mohor 8077d 02h /ethmac/trunk/rtl/verilog/eth_wishbone.v
61 RxStartFrm cleared when abort or retry comes. mohor 8077d 07h /ethmac/trunk/rtl/verilog/eth_wishbone.v

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