URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 272

Rev	Log message	Author	Age	Path
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	7948d 12h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
118	ShiftEnded synchronization changed.	mohor	7952d 03h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
115	RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.	mohor	7953d 11h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
113	RxPointer bug fixed.	mohor	7961d 01h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
112	Previous bug wasn't succesfully removed. Now fixed.	mohor	7961d 14h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
111	Master state machine had a bug when switching from master write to master read.	mohor	7962d 04h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
110	m_wb_cyc_o signal released after every single transfer.	mohor	7962d 07h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8029d 17h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8038d 19h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
97	Small typo fixed.	lampret	8064d 11h	/ethmac/trunk/rtl/verilog/eth_wishbone.v