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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 272

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Rev Log message Author Age Path
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 8114d 12h /ethmac/trunk/rtl/verilog/eth_wishbone.v
118 ShiftEnded synchronization changed. mohor 8118d 03h /ethmac/trunk/rtl/verilog/eth_wishbone.v
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 8119d 11h /ethmac/trunk/rtl/verilog/eth_wishbone.v
113 RxPointer bug fixed. mohor 8127d 01h /ethmac/trunk/rtl/verilog/eth_wishbone.v
112 Previous bug wasn't succesfully removed. Now fixed. mohor 8127d 14h /ethmac/trunk/rtl/verilog/eth_wishbone.v
111 Master state machine had a bug when switching from master write to
master read.
mohor 8128d 04h /ethmac/trunk/rtl/verilog/eth_wishbone.v
110 m_wb_cyc_o signal released after every single transfer. mohor 8128d 07h /ethmac/trunk/rtl/verilog/eth_wishbone.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8195d 17h /ethmac/trunk/rtl/verilog/eth_wishbone.v
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 8204d 19h /ethmac/trunk/rtl/verilog/eth_wishbone.v
97 Small typo fixed. lampret 8230d 11h /ethmac/trunk/rtl/verilog/eth_wishbone.v

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