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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 304

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Rev Log message Author Age Path
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.
mohor 8067d 12h /ethmac/trunk/rtl/verilog/eth_wishbone.v
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.
mohor 8071d 10h /ethmac/trunk/rtl/verilog/eth_wishbone.v
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.
mohor 8092d 09h /ethmac/trunk/rtl/verilog/eth_wishbone.v
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 8112d 11h /ethmac/trunk/rtl/verilog/eth_wishbone.v
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 8114d 14h /ethmac/trunk/rtl/verilog/eth_wishbone.v
118 ShiftEnded synchronization changed. mohor 8118d 04h /ethmac/trunk/rtl/verilog/eth_wishbone.v
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 8119d 13h /ethmac/trunk/rtl/verilog/eth_wishbone.v
113 RxPointer bug fixed. mohor 8127d 02h /ethmac/trunk/rtl/verilog/eth_wishbone.v
112 Previous bug wasn't succesfully removed. Now fixed. mohor 8127d 16h /ethmac/trunk/rtl/verilog/eth_wishbone.v
111 Master state machine had a bug when switching from master write to
master read.
mohor 8128d 05h /ethmac/trunk/rtl/verilog/eth_wishbone.v

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