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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 321

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Rev Log message Author Age Path
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries
igorm 6602d 14h /ethmac/trunk/rtl/verilog/eth_wishbone.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 6768d 11h /ethmac/trunk/rtl/verilog/eth_wishbone.v
302 mbist signals updated according to newest convention markom 6794d 22h /ethmac/trunk/rtl/verilog/eth_wishbone.v
280 Reset has priority in some flipflops. mohor 7054d 15h /ethmac/trunk/rtl/verilog/eth_wishbone.v
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.
mohor 7054d 16h /ethmac/trunk/rtl/verilog/eth_wishbone.v
272 When control packets were received, they were ignored in some cases. tadejm 7062d 16h /ethmac/trunk/rtl/verilog/eth_wishbone.v
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.
mohor 7063d 18h /ethmac/trunk/rtl/verilog/eth_wishbone.v
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7064d 18h /ethmac/trunk/rtl/verilog/eth_wishbone.v
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.
mohor 7123d 16h /ethmac/trunk/rtl/verilog/eth_wishbone.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 7124d 04h /ethmac/trunk/rtl/verilog/eth_wishbone.v
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 7126d 12h /ethmac/trunk/rtl/verilog/eth_wishbone.v
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7132d 08h /ethmac/trunk/rtl/verilog/eth_wishbone.v
229 case changed to casex. mohor 7158d 09h /ethmac/trunk/rtl/verilog/eth_wishbone.v
227 Changed BIST scan signals. tadejm 7158d 13h /ethmac/trunk/rtl/verilog/eth_wishbone.v
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7158d 14h /ethmac/trunk/rtl/verilog/eth_wishbone.v
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7162d 14h /ethmac/trunk/rtl/verilog/eth_wishbone.v
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 7165d 14h /ethmac/trunk/rtl/verilog/eth_wishbone.v
210 BIST added. mohor 7166d 13h /ethmac/trunk/rtl/verilog/eth_wishbone.v
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7195d 16h /ethmac/trunk/rtl/verilog/eth_wishbone.v
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.
mohor 7196d 16h /ethmac/trunk/rtl/verilog/eth_wishbone.v

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