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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 323

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Rev	Log message	Author	Age	Path
166	Reception is possible after RxPointer is read and not after BD is read. For that reason RxBDReady is changed to RxReady. Busy_IRQ interrupt connected. When there is no RxBD ready and frame comes, interrupt is generated.	mohor	7903d 19h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
164	Ethernet debug registers removed.	mohor	7903d 22h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
159	Async reset for WB_ACK_O removed (when core was in reset, it was impossible to access BDs). RxPointers and TxPointers names changed to be more descriptive. TxUnderRun synchronized.	mohor	7905d 16h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
150	Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal was not used OK.	mohor	7909d 14h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
134	Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No need to multiply or devide any more.	mohor	7930d 13h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
127	WriteRxDataToMemory signal changed so end of frame (when last word is written to fifo) is changed.	mohor	7950d 15h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	7952d 18h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
118	ShiftEnded synchronization changed.	mohor	7956d 08h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
115	RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.	mohor	7957d 17h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
113	RxPointer bug fixed.	mohor	7965d 06h	/ethmac/trunk/rtl/verilog/eth_wishbone.v

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