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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 354

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Rev Log message Author Age Path
354 Whitespace cleanup olof 3949d 10h /ethmac/trunk/rtl/verilog/eth_wishbone.v
352 Removed delayed assignments from rtl code olof 3955d 17h /ethmac/trunk/rtl/verilog/eth_wishbone.v
349 Make all parameters configurable from top level olof 3965d 08h /ethmac/trunk/rtl/verilog/eth_wishbone.v
346 Updated project location olof 3966d 10h /ethmac/trunk/rtl/verilog/eth_wishbone.v
338 root 4770d 12h /ethmac/trunk/rtl/verilog/eth_wishbone.v
335 New directory structure. root 4827d 18h /ethmac/trunk/rtl/verilog/eth_wishbone.v
333 Some small fixes + some troubles fixed. igorm 6276d 08h /ethmac/trunk/rtl/verilog/eth_wishbone.v
329 Defer indication fixed. igorm 6304d 16h /ethmac/trunk/rtl/verilog/eth_wishbone.v
323 Accidently deleted line put back. igorm 6601d 17h /ethmac/trunk/rtl/verilog/eth_wishbone.v
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries
igorm 6605d 12h /ethmac/trunk/rtl/verilog/eth_wishbone.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 6771d 09h /ethmac/trunk/rtl/verilog/eth_wishbone.v
302 mbist signals updated according to newest convention markom 6797d 20h /ethmac/trunk/rtl/verilog/eth_wishbone.v
280 Reset has priority in some flipflops. mohor 7057d 13h /ethmac/trunk/rtl/verilog/eth_wishbone.v
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.
mohor 7057d 14h /ethmac/trunk/rtl/verilog/eth_wishbone.v
272 When control packets were received, they were ignored in some cases. tadejm 7065d 14h /ethmac/trunk/rtl/verilog/eth_wishbone.v
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.
mohor 7066d 16h /ethmac/trunk/rtl/verilog/eth_wishbone.v
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7067d 16h /ethmac/trunk/rtl/verilog/eth_wishbone.v
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.
mohor 7126d 14h /ethmac/trunk/rtl/verilog/eth_wishbone.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 7127d 02h /ethmac/trunk/rtl/verilog/eth_wishbone.v
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 7129d 10h /ethmac/trunk/rtl/verilog/eth_wishbone.v

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