URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 364

Rev	Log message	Author	Age	Path
270	When receiving normal data frame and RxFlow control was switched on, RXB interrupt was not set.	mohor	7777d 05h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
269	When in full duplex, transmit was sometimes blocked. Fixed.	mohor	7778d 05h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
264	Registers RxStatusWrite_rck and RxStatusWriteLatched were not used anywhere. Removed.	mohor	7837d 04h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
261	Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort synchronized.	mohor	7837d 15h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
250	AddressMiss status is connecting to the Rx BD. AddressMiss is identifying that a frame was received because of the promiscous mode.	mohor	7840d 00h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	7845d 19h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
229	case changed to casex.	mohor	7871d 21h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
227	Changed BIST scan signals.	tadejm	7872d 00h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	7872d 02h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	7876d 01h	/ethmac/trunk/rtl/verilog/eth_wishbone.v