URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 77

Rev	Log message	Author	Age	Path
77	Interrupts changed	mohor	8109d 02h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
64	Status was not written correctly when frames were discarted because of address mismatch.	mohor	8120d 02h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
61	RxStartFrm cleared when abort or retry comes.	mohor	8120d 06h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
60	Changes that were lost when updating from 1.5 to 1.8 fixed.	mohor	8120d 07h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
54	Addition of new module eth_addrcheck.v	billditt	8120d 22h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
48	RxOverRun added to statuses.	mohor	8123d 02h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
43	Tx status is written back to the BD.	mohor	8124d 09h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
42	Rx status is written back to the BD.	mohor	8127d 02h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
41	non-DMA host interface added. Select the right configutation in eth_defines.	mohor	8129d 04h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
40	Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 MHz. Statuses, overrun, control frame transmission and reception still need to be fixed.	mohor	8130d 02h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
39	Tx part finished. TxStatus needs to be fixed. Pause request needs to be added.	mohor	8134d 06h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
38	Initial version. Equals to eth_wishbonedma.v at this moment.	mohor	8143d 08h	/ethmac/trunk/rtl/verilog/eth_wishbone.v