OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 91

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
91 Comments in Slovene language removed. mohor 8080d 11h /ethmac/trunk/rtl/verilog/eth_wishbone.v
90 casex changed with case, fifo reset changed. mohor 8080d 11h /ethmac/trunk/rtl/verilog/eth_wishbone.v
88 rx_fifo was not always cleared ok. Fixed. mohor 8090d 08h /ethmac/trunk/rtl/verilog/eth_wishbone.v
87 Status was not latched correctly sometimes. Fixed. mohor 8090d 10h /ethmac/trunk/rtl/verilog/eth_wishbone.v
86 Big Endian problem when sending frames fixed. mohor 8091d 17h /ethmac/trunk/rtl/verilog/eth_wishbone.v
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.		 mohor 8097d 05h /ethmac/trunk/rtl/verilog/eth_wishbone.v
80 Small fixes for external/internal DMA missmatches. mohor 8101d 07h /ethmac/trunk/rtl/verilog/eth_wishbone.v
77 Interrupts changed mohor 8101d 07h /ethmac/trunk/rtl/verilog/eth_wishbone.v
64 Status was not written correctly when frames were discarted because of
address mismatch.		 mohor 8112d 07h /ethmac/trunk/rtl/verilog/eth_wishbone.v
61 RxStartFrm cleared when abort or retry comes. mohor 8112d 11h /ethmac/trunk/rtl/verilog/eth_wishbone.v
60 Changes that were lost when updating from 1.5 to 1.8 fixed. mohor 8112d 12h /ethmac/trunk/rtl/verilog/eth_wishbone.v
54 Addition of new module eth_addrcheck.v billditt 8113d 03h /ethmac/trunk/rtl/verilog/eth_wishbone.v
48 RxOverRun added to statuses. mohor 8115d 07h /ethmac/trunk/rtl/verilog/eth_wishbone.v
43 Tx status is written back to the BD. mohor 8116d 14h /ethmac/trunk/rtl/verilog/eth_wishbone.v
42 Rx status is written back to the BD. mohor 8119d 07h /ethmac/trunk/rtl/verilog/eth_wishbone.v
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8121d 10h /ethmac/trunk/rtl/verilog/eth_wishbone.v
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.		 mohor 8122d 07h /ethmac/trunk/rtl/verilog/eth_wishbone.v
39 Tx part finished. TxStatus needs to be fixed. Pause request needs to be
added.		 mohor 8126d 11h /ethmac/trunk/rtl/verilog/eth_wishbone.v
38 Initial version. Equals to eth_wishbonedma.v at this moment. mohor 8135d 13h /ethmac/trunk/rtl/verilog/eth_wishbone.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.