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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 96

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Rev	Log message	Author	Age	Path
96	Any address can be used for Tx and Rx BD pointers. Address does not need to be aligned.	mohor	8080d 09h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
91	Comments in Slovene language removed.	mohor	8086d 13h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
90	casex changed with case, fifo reset changed.	mohor	8086d 13h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
88	rx_fifo was not always cleared ok. Fixed.	mohor	8096d 10h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
87	Status was not latched correctly sometimes. Fixed.	mohor	8096d 12h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
86	Big Endian problem when sending frames fixed.	mohor	8097d 19h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
82	Byte ordering changed (Big Endian used). casex changed with case because Xilinx Foundation had problems. Tested in HW. It WORKS.	mohor	8103d 06h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
80	Small fixes for external/internal DMA missmatches.	mohor	8107d 09h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
77	Interrupts changed	mohor	8107d 09h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
64	Status was not written correctly when frames were discarted because of address mismatch.	mohor	8118d 09h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
61	RxStartFrm cleared when abort or retry comes.	mohor	8118d 13h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
60	Changes that were lost when updating from 1.5 to 1.8 fixed.	mohor	8118d 14h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
54	Addition of new module eth_addrcheck.v	billditt	8119d 05h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
48	RxOverRun added to statuses.	mohor	8121d 09h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
43	Tx status is written back to the BD.	mohor	8122d 16h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
42	Rx status is written back to the BD.	mohor	8125d 09h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
41	non-DMA host interface added. Select the right configutation in eth_defines.	mohor	8127d 12h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
40	Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 MHz. Statuses, overrun, control frame transmission and reception still need to be fixed.	mohor	8128d 09h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
39	Tx part finished. TxStatus needs to be fixed. Pause request needs to be added.	mohor	8132d 13h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
38	Initial version. Equals to eth_wishbonedma.v at this moment.	mohor	8141d 15h	/ethmac/trunk/rtl/verilog/eth_wishbone.v

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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 96

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