URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 97

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
97	Small typo fixed.	lampret	8074d 14h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
96	Any address can be used for Tx and Rx BD pointers. Address does not need to be aligned.	mohor	8078d 14h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
91	Comments in Slovene language removed.	mohor	8084d 18h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
90	casex changed with case, fifo reset changed.	mohor	8084d 18h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
88	rx_fifo was not always cleared ok. Fixed.	mohor	8094d 14h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
87	Status was not latched correctly sometimes. Fixed.	mohor	8094d 17h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
86	Big Endian problem when sending frames fixed.	mohor	8095d 23h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
82	Byte ordering changed (Big Endian used). casex changed with case because Xilinx Foundation had problems. Tested in HW. It WORKS.	mohor	8101d 11h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
80	Small fixes for external/internal DMA missmatches.	mohor	8105d 13h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
77	Interrupts changed	mohor	8105d 14h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
64	Status was not written correctly when frames were discarted because of address mismatch.	mohor	8116d 13h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
61	RxStartFrm cleared when abort or retry comes.	mohor	8116d 18h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
60	Changes that were lost when updating from 1.5 to 1.8 fixed.	mohor	8116d 18h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
54	Addition of new module eth_addrcheck.v	billditt	8117d 09h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
48	RxOverRun added to statuses.	mohor	8119d 13h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
43	Tx status is written back to the BD.	mohor	8120d 21h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
42	Rx status is written back to the BD.	mohor	8123d 14h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
41	non-DMA host interface added. Select the right configutation in eth_defines.	mohor	8125d 16h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
40	Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 MHz. Statuses, overrun, control frame transmission and reception still need to be fixed.	mohor	8126d 14h	/ethmac/trunk/rtl/verilog/eth_wishbone.v
39	Tx part finished. TxStatus needs to be fixed. Pause request needs to be added.	mohor	8130d 18h	/ethmac/trunk/rtl/verilog/eth_wishbone.v

1 2 Next >

Show All

Browse

Tools

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 97

Filtering Options