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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac.v] - Rev 364

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Rev Log message Author Age Path
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 3291d 12h /ethmac/trunk/rtl/verilog/ethmac.v
360 Added partial implementation of the debug register from ORPSoC olof 3292d 20h /ethmac/trunk/rtl/verilog/eth_top.v
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 3296d 14h /ethmac/trunk/rtl/verilog/eth_top.v
352 Removed delayed assignments from rtl code olof 3302d 23h /ethmac/trunk/rtl/verilog/eth_top.v
349 Make all parameters configurable from top level olof 3312d 14h /ethmac/trunk/rtl/verilog/eth_top.v
346 Updated project location olof 3313d 16h /ethmac/trunk/rtl/verilog/eth_top.v
338 root 4117d 18h /ethmac/trunk/rtl/verilog/eth_top.v
335 New directory structure. root 4174d 23h /ethmac/trunk/rtl/verilog/eth_top.v
333 Some small fixes + some troubles fixed. igorm 5623d 13h /ethmac/trunk/rtl/verilog/eth_top.v
327 Defer indication fixed. igorm 5651d 22h /ethmac/trunk/rtl/verilog/eth_top.v
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries
igorm 5952d 18h /ethmac/trunk/rtl/verilog/eth_top.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 6118d 15h /ethmac/trunk/rtl/verilog/eth_top.v
302 mbist signals updated according to newest convention markom 6145d 01h /ethmac/trunk/rtl/verilog/eth_top.v
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 6155d 17h /ethmac/trunk/rtl/verilog/eth_top.v
276 Defer indication changed. tadejm 6404d 20h /ethmac/trunk/rtl/verilog/eth_top.v
272 When control packets were received, they were ignored in some cases. tadejm 6412d 19h /ethmac/trunk/rtl/verilog/eth_top.v
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.
mohor 6413d 21h /ethmac/trunk/rtl/verilog/eth_top.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 6474d 07h /ethmac/trunk/rtl/verilog/eth_top.v
255 TPauseRq synchronized to tx_clk. mohor 6475d 09h /ethmac/trunk/rtl/verilog/eth_top.v
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 6476d 15h /ethmac/trunk/rtl/verilog/eth_top.v

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