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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac.v] - Rev 364

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Rev Log message Author Age Path
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 7876d 20h /ethmac/trunk/rtl/verilog/ethmac.v
248 wb_rst_i is used for MIIM reset. mohor 7877d 20h /ethmac/trunk/rtl/verilog/ethmac.v
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7881d 19h /ethmac/trunk/rtl/verilog/ethmac.v
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7882d 15h /ethmac/trunk/rtl/verilog/ethmac.v
227 Changed BIST scan signals. tadejm 7908d 20h /ethmac/trunk/rtl/verilog/ethmac.v
218 Typo error fixed. (When using Bist) mohor 7916d 00h /ethmac/trunk/rtl/verilog/ethmac.v
214 Signals for WISHBONE B3 compliant interface added. mohor 7916d 20h /ethmac/trunk/rtl/verilog/ethmac.v
210 BIST added. mohor 7916d 21h /ethmac/trunk/rtl/verilog/ethmac.v
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 7936d 20h /ethmac/trunk/rtl/verilog/ethmac.v
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7944d 22h /ethmac/trunk/rtl/verilog/ethmac.v

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