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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac.v] - Rev 367

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Rev Log message Author Age Path
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 2963d 02h /ethmac/trunk/rtl/verilog/ethmac.v
365 Whitespace cleanup olof 3088d 05h /ethmac/trunk/rtl/verilog/ethmac.v
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 3089d 03h /ethmac/trunk/rtl/verilog/ethmac.v
360 Added partial implementation of the debug register from ORPSoC olof 3090d 11h /ethmac/trunk/rtl/verilog/eth_top.v
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 3094d 05h /ethmac/trunk/rtl/verilog/eth_top.v
352 Removed delayed assignments from rtl code olof 3100d 13h /ethmac/trunk/rtl/verilog/eth_top.v
349 Make all parameters configurable from top level olof 3110d 04h /ethmac/trunk/rtl/verilog/eth_top.v
346 Updated project location olof 3111d 06h /ethmac/trunk/rtl/verilog/eth_top.v
338 root 3915d 08h /ethmac/trunk/rtl/verilog/eth_top.v
335 New directory structure. root 3972d 14h /ethmac/trunk/rtl/verilog/eth_top.v
333 Some small fixes + some troubles fixed. igorm 5421d 04h /ethmac/trunk/rtl/verilog/eth_top.v
327 Defer indication fixed. igorm 5449d 13h /ethmac/trunk/rtl/verilog/eth_top.v
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries
igorm 5750d 08h /ethmac/trunk/rtl/verilog/eth_top.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 5916d 05h /ethmac/trunk/rtl/verilog/eth_top.v
302 mbist signals updated according to newest convention markom 5942d 16h /ethmac/trunk/rtl/verilog/eth_top.v
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 5953d 08h /ethmac/trunk/rtl/verilog/eth_top.v
276 Defer indication changed. tadejm 6202d 10h /ethmac/trunk/rtl/verilog/eth_top.v
272 When control packets were received, they were ignored in some cases. tadejm 6210d 10h /ethmac/trunk/rtl/verilog/eth_top.v
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.
mohor 6211d 12h /ethmac/trunk/rtl/verilog/eth_top.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 6271d 22h /ethmac/trunk/rtl/verilog/eth_top.v

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