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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac.v] - Rev 367

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Rev Log message Author Age Path
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 4601d 04h /ethmac/trunk/rtl/verilog/ethmac.v
365 Whitespace cleanup olof 4726d 07h /ethmac/trunk/rtl/verilog/ethmac.v
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 4727d 05h /ethmac/trunk/rtl/verilog/ethmac.v
360 Added partial implementation of the debug register from ORPSoC olof 4728d 12h /ethmac/trunk/rtl/verilog/eth_top.v
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4732d 06h /ethmac/trunk/rtl/verilog/eth_top.v
352 Removed delayed assignments from rtl code olof 4738d 15h /ethmac/trunk/rtl/verilog/eth_top.v
349 Make all parameters configurable from top level olof 4748d 06h /ethmac/trunk/rtl/verilog/eth_top.v
346 Updated project location olof 4749d 08h /ethmac/trunk/rtl/verilog/eth_top.v
338 root 5553d 10h /ethmac/trunk/rtl/verilog/eth_top.v
335 New directory structure. root 5610d 15h /ethmac/trunk/rtl/verilog/eth_top.v
333 Some small fixes + some troubles fixed. igorm 7059d 05h /ethmac/trunk/rtl/verilog/eth_top.v
327 Defer indication fixed. igorm 7087d 14h /ethmac/trunk/rtl/verilog/eth_top.v
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries
igorm 7388d 10h /ethmac/trunk/rtl/verilog/eth_top.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7554d 07h /ethmac/trunk/rtl/verilog/eth_top.v
302 mbist signals updated according to newest convention markom 7580d 18h /ethmac/trunk/rtl/verilog/eth_top.v
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 7591d 10h /ethmac/trunk/rtl/verilog/eth_top.v
276 Defer indication changed. tadejm 7840d 12h /ethmac/trunk/rtl/verilog/eth_top.v
272 When control packets were received, they were ignored in some cases. tadejm 7848d 12h /ethmac/trunk/rtl/verilog/eth_top.v
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.
mohor 7849d 13h /ethmac/trunk/rtl/verilog/eth_top.v
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.
mohor 7909d 23h /ethmac/trunk/rtl/verilog/eth_top.v
255 TPauseRq synchronized to tx_clk. mohor 7911d 01h /ethmac/trunk/rtl/verilog/eth_top.v
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7912d 07h /ethmac/trunk/rtl/verilog/eth_top.v
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.
mohor 7912d 08h /ethmac/trunk/rtl/verilog/eth_top.v
248 wb_rst_i is used for MIIM reset. mohor 7913d 08h /ethmac/trunk/rtl/verilog/eth_top.v
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7917d 07h /ethmac/trunk/rtl/verilog/eth_top.v
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7918d 03h /ethmac/trunk/rtl/verilog/eth_top.v
227 Changed BIST scan signals. tadejm 7944d 08h /ethmac/trunk/rtl/verilog/eth_top.v
218 Typo error fixed. (When using Bist) mohor 7951d 12h /ethmac/trunk/rtl/verilog/eth_top.v
214 Signals for WISHBONE B3 compliant interface added. mohor 7952d 09h /ethmac/trunk/rtl/verilog/eth_top.v
210 BIST added. mohor 7952d 09h /ethmac/trunk/rtl/verilog/eth_top.v

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