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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [ethmac_defines.v] - Rev 360


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Rev Log message Author Age Path
360 Added partial implementation of the debug register from ORPSoC olof 3935d 01h /ethmac/trunk/rtl/verilog/ethmac_defines.v
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 3938d 20h /ethmac/trunk/rtl/verilog/ethmac_defines.v
351 Turn defines into parameters in eth_cop olof 3953d 18h /ethmac/trunk/rtl/verilog/eth_defines.v
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3953d 19h /ethmac/trunk/rtl/verilog/eth_defines.v
346 Updated project location olof 3955d 21h /ethmac/trunk/rtl/verilog/eth_defines.v
338 root 4759d 23h /ethmac/trunk/rtl/verilog/eth_defines.v
335 New directory structure. root 4817d 05h /ethmac/trunk/rtl/verilog/eth_defines.v
330 Warning fixes. igorm 6294d 02h /ethmac/trunk/rtl/verilog/eth_defines.v
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 6760d 20h /ethmac/trunk/rtl/verilog/eth_defines.v
302 mbist signals updated according to newest convention markom 6787d 07h /ethmac/trunk/rtl/verilog/eth_defines.v
297 Artisan ram instance added. simons 6850d 22h /ethmac/trunk/rtl/verilog/eth_defines.v
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.
mohor 6913d 03h /ethmac/trunk/rtl/verilog/eth_defines.v
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7118d 21h /ethmac/trunk/rtl/verilog/eth_defines.v
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7123d 00h /ethmac/trunk/rtl/verilog/eth_defines.v
238 Defines fixed to use generic RAM by default. mohor 7136d 20h /ethmac/trunk/rtl/verilog/eth_defines.v
232 fpga define added. mohor 7144d 20h /ethmac/trunk/rtl/verilog/eth_defines.v
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7158d 22h /ethmac/trunk/rtl/verilog/eth_defines.v
211 Bist added. mohor 7158d 22h /ethmac/trunk/rtl/verilog/eth_defines.v
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
mohor 7175d 20h /ethmac/trunk/rtl/verilog/eth_defines.v
145 Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). mohor 7194d 20h /ethmac/trunk/rtl/verilog/eth_defines.v
137 Defines for register width added. mii_rst signal in MIIMODER register
mohor 7213d 17h /ethmac/trunk/rtl/verilog/eth_defines.v
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.
mohor 7215d 19h /ethmac/trunk/rtl/verilog/eth_defines.v
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7237d 23h /ethmac/trunk/rtl/verilog/eth_defines.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 7319d 04h /ethmac/trunk/rtl/verilog/eth_defines.v
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 7328d 06h /ethmac/trunk/rtl/verilog/eth_defines.v
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
mohor 7364d 02h /ethmac/trunk/rtl/verilog/eth_defines.v
73 Number of interrupts changed mohor 7384d 23h /ethmac/trunk/rtl/verilog/eth_defines.v
68 Registered trimmed. Unused registers removed. mohor 7395d 01h /ethmac/trunk/rtl/verilog/eth_defines.v
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 7395d 02h /ethmac/trunk/rtl/verilog/eth_defines.v
55 Changed that were lost with last update put back to the file. mohor 7396d 04h /ethmac/trunk/rtl/verilog/eth_defines.v

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