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[/] [ethmac/] [trunk/] [rtl/] [verilog/] [timescale.v] - Rev 24

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24 Log file added. mohor 7720d 07h /ethmac/trunk/rtl/verilog/timescale.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 7720d 10h /ethmac/trunk/rtl/verilog/timescale.v

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