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[/] [ethmac/] [trunk/] [rtl] - Rev 239

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Rev Log message Author Age Path
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7855d 21h /ethmac/trunk/rtl
238 Defines fixed to use generic RAM by default. mohor 7868d 01h /ethmac/trunk/rtl
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7870d 07h /ethmac/trunk/rtl
232 fpga define added. mohor 7876d 01h /ethmac/trunk/rtl
229 case changed to casex. mohor 7881d 23h /ethmac/trunk/rtl
227 Changed BIST scan signals. tadejm 7882d 03h /ethmac/trunk/rtl
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7882d 04h /ethmac/trunk/rtl
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7886d 04h /ethmac/trunk/rtl
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7889d 04h /ethmac/trunk/rtl
218 Typo error fixed. (When using Bist) mohor 7889d 06h /ethmac/trunk/rtl
214 Signals for WISHBONE B3 compliant interface added. mohor 7890d 03h /ethmac/trunk/rtl
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7890d 03h /ethmac/trunk/rtl
212 Minor $display change. mohor 7890d 03h /ethmac/trunk/rtl
211 Bist added. mohor 7890d 03h /ethmac/trunk/rtl
210 BIST added. mohor 7890d 03h /ethmac/trunk/rtl
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7907d 01h /ethmac/trunk/rtl
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7907d 01h /ethmac/trunk/rtl
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.		 mohor 7910d 03h /ethmac/trunk/rtl
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7918d 05h /ethmac/trunk/rtl
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7919d 05h /ethmac/trunk/rtl
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.		 mohor 7920d 06h /ethmac/trunk/rtl
165 HASH improvement needed. mohor 7920d 09h /ethmac/trunk/rtl
164 Ethernet debug registers removed. mohor 7920d 09h /ethmac/trunk/rtl
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.		 mohor 7921d 07h /ethmac/trunk/rtl
160 error acknowledge cycle termination added to display. mohor 7921d 07h /ethmac/trunk/rtl
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.		 mohor 7922d 03h /ethmac/trunk/rtl
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.		 mohor 7926d 01h /ethmac/trunk/rtl
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
connected.		 mohor 7926d 01h /ethmac/trunk/rtl
148 Bug when last byte of destination address was not checked fixed. mohor 7926d 01h /ethmac/trunk/rtl
147 ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
the control frames connected.		 mohor 7926d 01h /ethmac/trunk/rtl

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