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[/] [ethmac/] [trunk/] [rtl] - Rev 304

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Rev Log message Author Age Path
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7487d 03h /ethmac/trunk/rtl
302 mbist signals updated according to newest convention markom 7513d 14h /ethmac/trunk/rtl
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 7524d 06h /ethmac/trunk/rtl
297 Artisan ram instance added. simons 7577d 05h /ethmac/trunk/rtl
288 This file was not part of the RTL before, but it should be here. simons 7613d 06h /ethmac/trunk/rtl
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 7639d 09h /ethmac/trunk/rtl
285 Binary operator used instead of unary (xnor). mohor 7639d 10h /ethmac/trunk/rtl
284 Busy was set 2 cycles too late. Reported by Dennis Scott. mohor 7667d 11h /ethmac/trunk/rtl
283 RxBDAddress was updated also when value to r_TxBDNum was written with
greater value than allowed.		 mohor 7695d 05h /ethmac/trunk/rtl
280 Reset has priority in some flipflops. mohor 7773d 07h /ethmac/trunk/rtl
278 A new bug (entered with previous update) fixed. When abort occured sometimes
data transmission was blocked.		 mohor 7773d 08h /ethmac/trunk/rtl
277 When padding was enabled and crc disabled, frame was not ended correctly. mohor 7773d 08h /ethmac/trunk/rtl
276 Defer indication changed. tadejm 7773d 08h /ethmac/trunk/rtl
275 Fix MTxErr or prevent sending too big frames. mohor 7780d 12h /ethmac/trunk/rtl
272 When control packets were received, they were ignored in some cases. tadejm 7781d 08h /ethmac/trunk/rtl
270 When receiving normal data frame and RxFlow control was switched on, RXB
interrupt was not set.		 mohor 7782d 09h /ethmac/trunk/rtl
269 When in full duplex, transmit was sometimes blocked. Fixed. mohor 7783d 09h /ethmac/trunk/rtl
264 Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
anywhere. Removed.		 mohor 7842d 08h /ethmac/trunk/rtl
261 Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
synchronized.		 mohor 7842d 19h /ethmac/trunk/rtl
259 In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
of additional logic is necessery (FIFO for looping the data).		 mohor 7843d 21h /ethmac/trunk/rtl
257 When TxUsedData and CtrlMux occur at the same time, byte counter needs
to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.		 mohor 7843d 21h /ethmac/trunk/rtl
256 TxDone and TxAbort changed so they're not propagated to the wishbone
module when control frame is transmitted.		 mohor 7843d 21h /ethmac/trunk/rtl
255 TPauseRq synchronized to tx_clk. mohor 7843d 21h /ethmac/trunk/rtl
253 r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. mohor 7845d 03h /ethmac/trunk/rtl
251 When control frame (PAUSE) was sent, status was written in the
eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
Only TXC interrupt is set.		 mohor 7845d 04h /ethmac/trunk/rtl
250 AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
that a frame was received because of the promiscous mode.		 mohor 7845d 04h /ethmac/trunk/rtl
248 wb_rst_i is used for MIIM reset. mohor 7846d 04h /ethmac/trunk/rtl
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7849d 07h /ethmac/trunk/rtl
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7850d 03h /ethmac/trunk/rtl
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7850d 23h /ethmac/trunk/rtl

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