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[/] [ethmac/] [trunk/] [rtl] - Rev 367

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Rev Log message Author Age Path
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 4539d 23h /ethmac/trunk/rtl
366 Readded eth_top.v with a deprecation warning olof 4664d 02h /ethmac/trunk/rtl
365 Whitespace cleanup olof 4665d 02h /ethmac/trunk/rtl
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 4665d 23h /ethmac/trunk/rtl
360 Added partial implementation of the debug register from ORPSoC olof 4667d 07h /ethmac/trunk/rtl
359 Verilator linting fixes olof 4669d 09h /ethmac/trunk/rtl
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4670d 23h /ethmac/trunk/rtl
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4670d 23h /ethmac/trunk/rtl
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4671d 01h /ethmac/trunk/rtl
355 Import Julius Baxter's verilator hints from ORPSoC olof 4671d 02h /ethmac/trunk/rtl
354 Whitespace cleanup olof 4671d 02h /ethmac/trunk/rtl
353 Inherit fixes for bit width of constants from ORPSoC olof 4673d 04h /ethmac/trunk/rtl
352 Removed delayed assignments from rtl code olof 4677d 10h /ethmac/trunk/rtl
351 Turn defines into parameters in eth_cop olof 4685d 23h /ethmac/trunk/rtl
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4686d 00h /ethmac/trunk/rtl
349 Make all parameters configurable from top level olof 4687d 01h /ethmac/trunk/rtl
346 Updated project location olof 4688d 02h /ethmac/trunk/rtl
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4698d 02h /ethmac/trunk/rtl
338 root 5492d 05h /ethmac/trunk/rtl
335 New directory structure. root 5549d 10h /ethmac/trunk/rtl

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