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[/] [ethmac/] [trunk/] [sim/] - Rev 358


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Rev Log message Author Age Path
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4506d 12h /ethmac/trunk/sim/
338 root 5327d 16h /ethmac/trunk/sim/
335 New directory structure. root 5384d 21h /ethmac/trunk/sim/
319 Latest Ethernet IP core testbench. tadejm 7193d 15h /ethmac/trunk/sim/
311 Update script for running different file list files for different RAM models. tadejm 7305d 18h /ethmac/trunk/sim/
310 More signals. tadejm 7305d 18h /ethmac/trunk/sim/
309 Update file list files for different RAM models with byte select accessing. tadejm 7305d 18h /ethmac/trunk/sim/
308 Moved RAM model file path from sim_file_list.lst to this file. tadejm 7305d 18h /ethmac/trunk/sim/
299 Artisan RAMs added. mohor 7412d 19h /ethmac/trunk/sim/
295 Few minor changes. tadejm 7419d 17h /ethmac/trunk/sim/
294 Added path to a file with distributed RAM instances for xilinx. tadejm 7421d 18h /ethmac/trunk/sim/
293 initial. tadejm 7445d 15h /ethmac/trunk/sim/
292 Corrected mistake. tadejm 7445d 15h /ethmac/trunk/sim/
291 initial tadejm 7445d 16h /ethmac/trunk/sim/
290 Additional checking for FAILED tests added - for ATS. tadejm 7445d 17h /ethmac/trunk/sim/
225 Some minor changes. tadejm 7718d 15h /ethmac/trunk/sim/
224 Signals for a wave window in Modelsim. tadejm 7718d 17h /ethmac/trunk/sim/
217 Bist supported. mohor 7725d 17h /ethmac/trunk/sim/
215 Bist supported. mohor 7725d 18h /ethmac/trunk/sim/
208 Virtual Silicon RAMs moved to lib directory tadej 7743d 11h /ethmac/trunk/sim/

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