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[/] [ethmac/] [trunk/] [sim/] [rtl_sim/] - Rev 299

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Rev Log message Author Age Path
299 Artisan RAMs added. mohor 7779d 23h /ethmac/trunk/sim/rtl_sim/
295 Few minor changes. tadejm 7786d 21h /ethmac/trunk/sim/rtl_sim/
294 Added path to a file with distributed RAM instances for xilinx. tadejm 7788d 22h /ethmac/trunk/sim/rtl_sim/
293 initial. tadejm 7812d 19h /ethmac/trunk/sim/rtl_sim/
292 Corrected mistake. tadejm 7812d 19h /ethmac/trunk/sim/rtl_sim/
291 initial tadejm 7812d 20h /ethmac/trunk/sim/rtl_sim/
290 Additional checking for FAILED tests added - for ATS. tadejm 7812d 21h /ethmac/trunk/sim/rtl_sim/
225 Some minor changes. tadejm 8085d 19h /ethmac/trunk/sim/rtl_sim/
224 Signals for a wave window in Modelsim. tadejm 8085d 21h /ethmac/trunk/sim/rtl_sim/
217 Bist supported. mohor 8092d 21h /ethmac/trunk/sim/rtl_sim/
215 Bist supported. mohor 8092d 22h /ethmac/trunk/sim/rtl_sim/
208 Virtual Silicon RAMs moved to lib directory tadej 8110d 16h /ethmac/trunk/sim/rtl_sim/
207 Virtual Silicon RAM support fixed tadej 8110d 16h /ethmac/trunk/sim/rtl_sim/
206 Virtual Silicon RAM added to the simulation. mohor 8110d 16h /ethmac/trunk/sim/rtl_sim/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 8110d 17h /ethmac/trunk/sim/rtl_sim/
187 _info file added. mohor 8116d 15h /ethmac/trunk/sim/rtl_sim/
186 Macro for testbench (DO file). mohor 8116d 16h /ethmac/trunk/sim/rtl_sim/
185 Directory keeper. mohor 8116d 16h /ethmac/trunk/sim/rtl_sim/
184 Modelsim simulation environment should be ready now. mohor 8116d 16h /ethmac/trunk/sim/rtl_sim/
183 Modelsim environment added. mohor 8116d 17h /ethmac/trunk/sim/rtl_sim/

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