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[/] [ethmac] - Rev 368


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Rev Log message Author Age Path
368 dbg_dat0 only exist when `DEBUG_WISHBONE is set olof 2776d 11h /ethmac
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 2839d 08h /ethmac
366 Readded eth_top.v with a deprecation warning olof 2963d 12h /ethmac
365 Whitespace cleanup olof 2964d 11h /ethmac
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 2965d 09h /ethmac
363 quartus project files unneback 2965d 17h /ethmac
362 added Makefiles to build project unneback 2965d 18h /ethmac
361 created branch unneback unneback 2965d 18h /ethmac
360 Added partial implementation of the debug register from ORPSoC olof 2966d 16h /ethmac
359 Verilator linting fixes olof 2968d 19h /ethmac
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 2970d 09h /ethmac
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 2970d 09h /ethmac
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 2970d 11h /ethmac
355 Import Julius Baxter's verilator hints from ORPSoC olof 2970d 11h /ethmac
354 Whitespace cleanup olof 2970d 12h /ethmac
353 Inherit fixes for bit width of constants from ORPSoC olof 2972d 13h /ethmac
352 Removed delayed assignments from rtl code olof 2976d 19h /ethmac
351 Turn defines into parameters in eth_cop olof 2985d 09h /ethmac
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 2985d 10h /ethmac
349 Make all parameters configurable from top level olof 2986d 10h /ethmac

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