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[/] [ethmac] - Rev 368


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Rev Log message Author Age Path
368 dbg_dat0 only exist when `DEBUG_WISHBONE is set olof 2902d 08h /ethmac
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 2965d 05h /ethmac
366 Readded eth_top.v with a deprecation warning olof 3089d 09h /ethmac
365 Whitespace cleanup olof 3090d 08h /ethmac
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 3091d 05h /ethmac
363 quartus project files unneback 3091d 14h /ethmac
362 added Makefiles to build project unneback 3091d 14h /ethmac
361 created branch unneback unneback 3091d 14h /ethmac
360 Added partial implementation of the debug register from ORPSoC olof 3092d 13h /ethmac
359 Verilator linting fixes olof 3094d 15h /ethmac
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 3096d 05h /ethmac
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 3096d 05h /ethmac
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 3096d 07h /ethmac
355 Import Julius Baxter's verilator hints from ORPSoC olof 3096d 08h /ethmac
354 Whitespace cleanup olof 3096d 08h /ethmac
353 Inherit fixes for bit width of constants from ORPSoC olof 3098d 10h /ethmac
352 Removed delayed assignments from rtl code olof 3102d 16h /ethmac
351 Turn defines into parameters in eth_cop olof 3111d 06h /ethmac
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3111d 06h /ethmac
349 Make all parameters configurable from top level olof 3112d 07h /ethmac

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