OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac] - Rev 361

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
361 created branch unneback unneback 4643d 15h /ethmac
360 Added partial implementation of the debug register from ORPSoC olof 4644d 14h /ethmac
359 Verilator linting fixes olof 4646d 16h /ethmac
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4648d 06h /ethmac
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4648d 06h /ethmac
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4648d 08h /ethmac
355 Import Julius Baxter's verilator hints from ORPSoC olof 4648d 09h /ethmac
354 Whitespace cleanup olof 4648d 09h /ethmac
353 Inherit fixes for bit width of constants from ORPSoC olof 4650d 11h /ethmac
352 Removed delayed assignments from rtl code olof 4654d 17h /ethmac
351 Turn defines into parameters in eth_cop olof 4663d 06h /ethmac
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4663d 07h /ethmac
349 Make all parameters configurable from top level olof 4664d 08h /ethmac
348 Added option to dump VCD files olof 4665d 07h /ethmac
347 Added information about running with Icarus Verilog olof 4665d 07h /ethmac
346 Updated project location olof 4665d 09h /ethmac
345 Temporarily disable failing tests olof 4665d 11h /ethmac
344 bit 9 in phy control register is self clearing olof 4671d 13h /ethmac
343 Address miss should not be asserted on short frames olof 4675d 09h /ethmac
342 Added cast to avoid inequality when comparing different data types olof 4675d 09h /ethmac

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.