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Rev Log message Author Age Path
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 7469d 01h /
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 7469d 01h /
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 7469d 01h /
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 7469d 01h /
99 Document revised. mohor 7476d 00h /
98 Document revised. mohor 7476d 00h /
97 Small typo fixed. lampret 7492d 23h /
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.
mohor 7496d 23h /
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.
mohor 7497d 01h /
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.
mohor 7497d 01h /
93 When in promiscous mode some frames were not received correctly. Fixed. mohor 7502d 00h /
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
mohor 7503d 02h /
91 Comments in Slovene language removed. mohor 7503d 02h /
90 casex changed with case, fifo reset changed. mohor 7503d 02h /
89 TX_BD_NUM, MAC_ADDR0 and MAC_ADDR1 register description
mohor 7507d 00h /
88 rx_fifo was not always cleared ok. Fixed. mohor 7512d 23h /
87 Status was not latched correctly sometimes. Fixed. mohor 7513d 01h /
86 Big Endian problem when sending frames fixed. mohor 7514d 08h /
85 Log info was missing. mohor 7519d 18h /
84 LinkFail signal was not latching appropriate bit. mohor 7519d 18h /

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