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Rev	Log message	Author	Age	Path
112	Previous bug wasn't succesfully removed. Now fixed.	mohor	7961d 03h	/
111	Master state machine had a bug when switching from master write to master read.	mohor	7961d 17h	/
110	m_wb_cyc_o signal released after every single transfer.	mohor	7961d 20h	/
109	Comment removed.	mohor	7961d 20h	/
108	Testbench supports unaligned accesses.	mohor	8029d 06h	/
107	TX_BUF_BASE changed.	mohor	8029d 06h	/
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8029d 06h	/
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8038d 08h	/
104	FCS should not be included in NibbleMinFl.	mohor	8040d 02h	/
103	Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is selected in eth_defines.v	mohor	8040d 02h	/
102	Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled or not.	mohor	8040d 03h	/
101	Short frame and ReceivedLengthOK were not detected correctly.	mohor	8040d 03h	/
100	Generic ram or Xilinx ram can be used in fifo (selectable by setting ETH_FIFO_XILINX in eth_defines.v).	mohor	8040d 03h	/
99	Document revised.	mohor	8047d 02h	/
98	Document revised.	mohor	8047d 02h	/
97	Small typo fixed.	lampret	8064d 00h	/
96	Any address can be used for Tx and Rx BD pointers. Address does not need to be aligned.	mohor	8068d 00h	/
95	md_padoen_o changed to md_padoe_o. Signal was always active high, just name was incorrect.	mohor	8068d 03h	/
94	When clear and read/write are active at the same time, cnt and pointers are set to 1.	mohor	8068d 03h	/
93	When in promiscous mode some frames were not received correctly. Fixed.	mohor	8073d 01h	/

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Subversion Repositories ethmac

[/] - Rev 112

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