OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 122

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7004d 13h /
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7004d 13h /
120 Unused files removed. mohor 7004d 14h /
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7004d 14h /
118 ShiftEnded synchronization changed. mohor 7008d 05h /
117 Clock mrx_clk set to 2.5 MHz. mohor 7008d 15h /
116 Testing environment also includes traffic cop, memory interface and host
interface.
mohor 7008d 15h /
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7009d 13h /
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7010d 10h /
113 RxPointer bug fixed. mohor 7017d 02h /
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7017d 16h /
111 Master state machine had a bug when switching from master write to
master read.
mohor 7018d 05h /
110 m_wb_cyc_o signal released after every single transfer. mohor 7018d 09h /
109 Comment removed. mohor 7018d 09h /
108 Testbench supports unaligned accesses. mohor 7085d 19h /
107 TX_BUF_BASE changed. mohor 7085d 19h /
106 Outputs registered. Reset changed for eth_wishbone module. mohor 7085d 19h /
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 7094d 20h /
104 FCS should not be included in NibbleMinFl. mohor 7096d 14h /
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 7096d 15h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.