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15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.		 mohor 8299d 07h /
14 Unconnected signals are now connected. mohor 8303d 12h /
13 New directory structure. Files upodated and put together. mohor 8305d 21h /
12 Directory structure changed. Files checked and joind together. mohor 8306d 00h /
11 Directory structure changed. Files checked and joind together. mohor 8306d 00h /
10 Directory structure changed. Files checked and joind together. mohor 8306d 00h /
9 Documentation updated to be synchronized to the verilog files. mohor 8333d 09h /
8 Version 1.3. Status registers added. DMA channels 2 and 3 are not used
any more. Things that are implementation specific were deleted out of the
document.		 mohor 8360d 13h /
7 Version 1.3. Status registers added. DMA channels 2 and 3 are not used
any more. Things that are implementation specific were deleted out of the
document.		 mohor 8360d 14h /
6 no message mohor 8360d 14h /
5 This is a Microsoft version of the spec in the pdf format. mohor 8364d 23h /
4 deleted mohor 8364d 23h /
3 This commit was manufactured by cvs2svn to create tag 'arelease'. 8436d 23h /
2 no message mohor 8436d 23h /
1 Standard project directories initialized by cvs2svn. 8436d 23h /

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