URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 158

Rev	Log message	Author	Age	Path
138	Synchronous reset added.	mohor	7923d 06h	/
137	Defines for register width added. mii_rst signal in MIIMODER register changed.	mohor	7923d 06h	/
136	Parameter ResetValue changed to capital letters.	mohor	7923d 16h	/
135	New revision. External DMA removed, TX_BD_NUM changed.	mohor	7925d 08h	/
134	Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No need to multiply or devide any more.	mohor	7925d 09h	/
133	- Busy signal was not set on time when scan status operation was performed and clock was divided with more than 2. - Nvalid remains valid two more clocks (was previously cleared too soon).	mohor	7925d 10h	/
132	LinkFailRegister is reflecting the status of the PHY's link fail status bit.	mohor	7925d 10h	/
131	LinkFail signal was not latching appropriate bit.	mohor	7925d 10h	/
130	First draft of the Ethernet design document. Not a finished version. Still many things missing.	mohor	7925d 10h	/
129	Traffic cop with 2 wishbone master interfaces and 2 wishbona slave interfaces: - Host connects to the master interface - Ethernet master (DMA) connects to the second master interface - Memory interface connects to the slave interface - Ethernet slave interface (access to registers and BDs) connects to second slave interface	mohor	7925d 11h	/