OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 163

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
163 Another temporary version. Core is almost finished. Testbench not included,
yet"
mohor 8165d 01h /
162 Another temporary version. Core is almost finished. Testbench not included,
yet.
mohor 8165d 01h /
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.
mohor 8165d 06h /
160 error acknowledge cycle termination added to display. mohor 8165d 06h /
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.
mohor 8166d 03h /
158 Typo fixed. mohor 8166d 03h /
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 8168d 08h /
156 Valid testbench. mohor 8168d 08h /
155 Minor changes. mohor 8168d 08h /
154 Design document is still under construction. mohor 8169d 08h /
153 Temp version (backup). mohor 8169d 23h /
152 Version 1.16 created. See revision history in the document for details. mohor 8169d 23h /
151 This commit was manufactured by cvs2svn to create tag 'rel_4'. 8170d 01h /
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.
mohor 8170d 01h /
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
connected.
mohor 8170d 01h /
148 Bug when last byte of destination address was not checked fixed. mohor 8170d 01h /
147 ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
the control frames connected.
mohor 8170d 01h /
146 CarrierSenseLost status is not set when working in loopback mode. mohor 8170d 01h /
145 Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). mohor 8170d 01h /
144 This commit was manufactured by cvs2svn to create tag
'runing_under_uclinux'.
8186d 03h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.