OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 203

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 7066d 12h /
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 7069d 13h /
201 Core size added to the document. mohor 7069d 14h /
200 File with lower case checked in instead. mohor 7069d 14h /
199 Datasheet name changed to lower case name. mohor 7069d 14h /
198 Removed file. File with name in lower case will be added instead. mohor 7069d 14h /
197 Ethernet Data Sheet. mohor 7069d 14h /
196 Ethernet product brief. mohor 7069d 15h /
195 Product brief removed because it is the same as Datasheet. mohor 7069d 15h /
194 Full duplex tests modified and testbench bug repaired. tadej 7069d 16h /
193 Temp version (backup). mohor 7069d 17h /
192 Some additional reports added tadej 7071d 12h /
191 Bug repaired in eth_phy device tadej 7071d 12h /
190 Several information added to the file. mohor 7071d 13h /
189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).
mohor 7071d 13h /
188 PHY changed. tadej 7072d 10h /
187 _info file added. mohor 7072d 10h /
186 Macro for testbench (DO file). mohor 7072d 11h /
185 Directory keeper. mohor 7072d 11h /
184 Modelsim simulation environment should be ready now. mohor 7072d 11h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.