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222 This commit was manufactured by cvs2svn to create tag 'rel_6'. 6183d 12h /
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6183d 12h /
220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 6186d 12h /
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6186d 12h /
218 Typo error fixed. (When using Bist) mohor 6186d 14h /
217 Bist supported. mohor 6186d 14h /
216 Bist signals added. mohor 6186d 14h /
215 Bist supported. mohor 6186d 15h /
214 Signals for WISHBONE B3 compliant interface added. mohor 6187d 11h /
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 6187d 11h /
212 Minor $display change. mohor 6187d 11h /
211 Bist added. mohor 6187d 11h /
210 BIST added. mohor 6187d 11h /
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 6188d 14h /
208 Virtual Silicon RAMs moved to lib directory tadej 6204d 08h /
207 Virtual Silicon RAM support fixed tadej 6204d 08h /
206 Virtual Silicon RAM added to the simulation. mohor 6204d 09h /
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 6204d 09h /
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 6204d 09h /
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 6204d 09h /

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