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237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 6416d 10h /
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6416d 10h /
235 rev 4. mohor 6417d 00h /
234 Figure list assed to the revision 3. mohor 6417d 08h /
233 Revision 0.3 released. Some figures added. mohor 6417d 09h /
232 fpga define added. mohor 6422d 04h /
231 Description of Core Modules added (figure). mohor 6424d 05h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 6428d 02h /
229 case changed to casex. mohor 6428d 02h /
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 6428d 05h /
227 Changed BIST scan signals. tadejm 6428d 05h /
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6428d 07h /
225 Some minor changes. tadejm 6428d 07h /
224 Signals for a wave window in Modelsim. tadejm 6428d 08h /
223 Some code changed due to bug fixes. tadejm 6428d 09h /
222 This commit was manufactured by cvs2svn to create tag 'rel_6'. 6432d 06h /
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6432d 06h /
220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 6435d 07h /
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6435d 07h /
218 Typo error fixed. (When using Bist) mohor 6435d 09h /

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