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Rev Log message Author Age Path
238 Defines fixed to use generic RAM by default. mohor 7275d 20h /
237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 7278d 02h /
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7278d 02h /
235 rev 4. mohor 7278d 16h /
234 Figure list assed to the revision 3. mohor 7279d 00h /
233 Revision 0.3 released. Some figures added. mohor 7279d 01h /
232 fpga define added. mohor 7283d 20h /
231 Description of Core Modules added (figure). mohor 7285d 21h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7289d 18h /
229 case changed to casex. mohor 7289d 18h /
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7289d 21h /
227 Changed BIST scan signals. tadejm 7289d 21h /
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7289d 23h /
225 Some minor changes. tadejm 7289d 23h /
224 Signals for a wave window in Modelsim. tadejm 7290d 00h /
223 Some code changed due to bug fixes. tadejm 7290d 01h /
222 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7293d 22h /
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7293d 22h /
220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7296d 23h /
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 7296d 23h /

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