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Rev Log message Author Age Path
238 Defines fixed to use generic RAM by default. mohor 7336d 00h /
237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 7338d 05h /
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7338d 05h /
235 rev 4. mohor 7338d 20h /
234 Figure list assed to the revision 3. mohor 7339d 04h /
233 Revision 0.3 released. Some figures added. mohor 7339d 04h /
232 fpga define added. mohor 7343d 23h /
231 Description of Core Modules added (figure). mohor 7346d 01h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7349d 21h /
229 case changed to casex. mohor 7349d 21h /
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7350d 01h /
227 Changed BIST scan signals. tadejm 7350d 01h /
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7350d 02h /
225 Some minor changes. tadejm 7350d 03h /
224 Signals for a wave window in Modelsim. tadejm 7350d 04h /
223 Some code changed due to bug fixes. tadejm 7350d 04h /
222 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7354d 02h /
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7354d 02h /
220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7357d 03h /
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 7357d 03h /
218 Typo error fixed. (When using Bist) mohor 7357d 04h /
217 Bist supported. mohor 7357d 05h /
216 Bist signals added. mohor 7357d 05h /
215 Bist supported. mohor 7357d 05h /
214 Signals for WISHBONE B3 compliant interface added. mohor 7358d 01h /
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7358d 01h /
212 Minor $display change. mohor 7358d 01h /
211 Bist added. mohor 7358d 02h /
210 BIST added. mohor 7358d 02h /
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7359d 05h /

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